August 16, 2018Fattorun

Linear Amplifier Scaling for Minimum Power Dissipation

The problem to solve is this: when designing a linear amplifier for a particular output-referred third-order intercept point (OIP3), what is the optimum output stage periphery and scaling factor that will achieve the target OIP3 with minimum DC power consumption?

Consider an infinite cascade of amplifier stages with equal gain per stage, g. The gate width of each transistor is scaled from the preceding stage by a uniform scaling factor, s. All stages are biased class A with the same drain voltage and the same current density such that the drain currents are also scaled by s.

Let’s assume the OIP3 for each transistor is 10 dB above P_{Cripps}, where

P_{Cripps}=\frac{I_{dq}}{2}\left ( V_{dd}-V_{knee} \right )

OIP3=\frac{10\times I_{dq}}{2}\left ( V_{dd}-V_{knee} \right )

It is usual to assume that intermodulation adds constructively in an amplifier cascade such that

\frac{1}{OIP3_{total}}=\frac{1}{OIP3_{n}}+\frac{1}{g_{n}\times OIP3_{n-1}}+\frac{1}{g_{n}\times g_{n-1}\times OIP3_{n-2}}+...

In our amplifier cascade the individual stage intercept points are related according to the gate width (drain current) scaling factor:

OIP3_{n}=s\times OIP3_{n-1}

And we assume that all stages, regardless of gate periphery, have the same small-signal gain:

g_{n}=g_{n-1}=g

The cascaded OIP3 can then be restated as

\frac{1}{OIP3_{total}}=\frac{1}{OIP3_{n}}\left ( 1+ \frac{s}{g}+\frac{s^{2}}{g^{2}}+... \right )=\frac{1}{OIP3_{n}}\sum_{i=0}^{n}\left ( \frac{s}{g} \right )^{i}

For an infinite cascade this is a geometric series which converges provided \left | \frac{s}{g} \right | < 1 (i.e. provided the gain per stage exceeds the scaling factor). The OIP3 of the infinite cascade can therefore be simplified to

\frac{1}{OIP3_{total}}=\frac{1}{OIP3_{n}\left ( 1-\frac{s}{g} \right )}
OIP3_{total}=OIP3_{n}\left ( 1-\frac{s}{g} \right )

The total DC power consumption is given by another series

P_{DC}=V_{dd}I_{dqn}\left ( 1+\frac{1}{s}+\frac{1}{s^{2}}+... \right )=V_{dd}I_{dqn}\sum_{i=0}^{n}\left ( \frac{1}{s} \right )^{i}

For an infinite cascade the total DC power consumption is

P_{DC}=\frac{V_{Vdd}I_{Idqn}}{1-\frac{1}{s}}

We want to maximise the ratio of OIP3_{total} to P_{DC}

\frac{OIP3_{total}}{P_{DC}}=\frac{OIP3_{n}\left ( 1-\frac{s}{g} \right )\left ( 1-\frac{1}{s} \right )}{V_{dd}I_{dqn}}

\frac{OIP3_{total}}{P_{DC}}=\frac{OIP3_{n}}{V_{dd}I_{dqn}}\left ( 1-\frac{s}{g}-\frac{1}{s}+\frac{1}{g} \right )

oip3_Pdc_SF.png

Take the derivative with respect to scaling factor, s

\frac{\mathrm{d} }{\mathrm{d} s}\left ( \frac{OIP3_{total}}{P_{DC}} \right )=\frac{OIP3_{n}}{V_{dd}I_{dqn}}\left ( \frac{1}{s^{2}}-\frac{1}{g} \right )

The ratio of OIP3_{total} to P_{DC} is maximised when

\frac{1}{s^{2}}-\frac{1}{g}=0

So to maximise the overall efficiency we find

s=\sqrt{g}

SF_gain_per_stage.png

and the final stage must be sized to achieve the required OIP3:

OIP3_{n}=\frac{OIP3_{total}}{\left ( 1-\frac{s}{g} \right )}=\frac{OIP3_{total}}{\left ( 1-\frac{1}{\sqrt{g}} \right )}

I_{dqn}=\frac{2 \times OIP3_{total}}{10\left ( V_{dd}-V_{knee} \right )\left ( 1-\frac{1}{\sqrt{g}} \right )}

In practice, these calculations provide lower bounds on scaling factor and FET periphery. The final stage may be optimised for linearity alone. However, the matching of preceding stages is usually compromised to achieve gain flatness, bandwidth etc. They will therefore require additional margin.
 

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